Everspin Demonstrates CXL-Connected MRAM Persistent Memory

Everspin Technologies demonstrated a Compute Express Link-connected MRAM platform at SNIA Developer Conference 2026. The system exposes non-volatile PERSYST MRAM through CXL with memory semantics, positioning it as a persistent tier between conventional DRAM and NAND-based storage rather than as a replacement for either one.

The September 29 demonstration is more concrete than a roadmap announcement: Everspin says the platform is working and ready for customers to test with their own workloads. The company demonstrated read and write access through the CXL interface, but it has not announced a retail PC product, broad commercial deployment, capacity roadmap or price for the CXL platform.

Everspin's demonstration used a Supermicro AS-1116CS-TN server with an AMD EPYC 9355 32-core processor. An AMD Alveo U250 FPGA platform carried a Wolley CXL controller, while the persistent-memory side used Everspin PERSYST 1GB DDR4 MRAM UDIMMs.

That composition matters because this is not a drop-in consumer DDR5 DIMM demonstration. CXL provides the coherent connectivity layer, the FPGA/controller bridges the memory into that environment, and the MRAM modules provide non-volatile storage with RAM-like access characteristics. The prototype therefore demonstrates an architecture and interoperability path rather than a finished mainstream memory product.

Conventional system DRAM loses its contents when power is removed. Everspin's MRAM retains data, so the company is targeting workloads where keeping frequently updated state close to compute can avoid first flushing that state to NAND storage. Everspin specifically points to persistent buffering, caching, metadata, AI checkpointing and persistent key-value cache as possible uses.

Everspin says the platform provides cache-line-level, nanosecond-class access and writes up to 100 times faster than NAND-based solid-state storage. Those are manufacturer claims from the demonstration announcement, not independent measurements by Core Tech Tips. They also do not establish that every workload would see a 100x application-level speedup.

MRAM persistence is not new by itself. The significance of this demonstration is the use of CXL as a standards-based path for making persistent MRAM available to modern compute platforms with memory semantics. Everspin says the architecture can also support pooling and sharing memory resources across hosts, allowing capacity to be assigned where workloads need it.

The next useful evidence will come from customer workload testing rather than another peak specification. Capacity, controller overhead, read and write behavior, endurance, software integration, power, cost and application-level performance will determine where a persistent MRAM tier is actually competitive with DRAM plus NAND-based storage.