Technical guide
PCIe ASPM Explained: L0, L0s, L1, L1.1, L1.2, Power, and Latency
Understand PCI Express Active State Power Management, the L0, L0s and L1 link states, L1 substates, Windows and Linux controls, and the real power-versus-latency tradeoff.
On this page
- ASPM saves power on an active PCIe link
- L0 is active; L0s and L1 trade idle power for wake latency
- L1.1 and L1.2 extend the L1 power-saving model
- Windows exposes link-state policy through the power framework
- Linux can manage ASPM, but firmware remains part of the picture
- ASPM is not the same thing as PCIe speed, width, or device power state
- When changing ASPM is actually useful
ASPM saves power on an active PCIe link
Active State Power Management, or ASPM, is PCI Express link power management. It allows a PCIe link to enter lower-power states while the attached devices remain logically available, then return to the fully active L0 state when traffic resumes.
That makes ASPM different from putting an entire device into a device power state or removing power from a slot. The link itself is the object being managed. Firmware, operating-system policy, endpoint capabilities and the upstream component all participate in deciding which supported states can be used.
| State | Role | Power / latency direction |
|---|---|---|
| L0 | Normal active link; transactions can flow | Highest active-link power, no ASPM wake transition |
| L0s | Shallow standby state used by ASPM | Lower power with relatively fast return to L0 |
| L1 | Deeper standby state | Greater saving opportunity with higher exit latency than L0s |
| L1.1 / L1.2 | L1 substates that permit progressively deeper link power saving | Can reduce idle power further; exact support and transition behavior are platform-specific |
| L2/L3 Ready | Preparation for deeper power removal states | Not the normal active-idle ASPM state |
L0 is active; L0s and L1 trade idle power for wake latency
PCI Express defines L0 as the normal operating link state. L0s is a shallow low-power standby intended for quick return to L0, while L1 is a deeper standby state that can disable more link circuitry and therefore carries a larger transition cost.
The important engineering tradeoff is not simply on versus off. A platform can save link power during idle periods at the cost of some exit latency when new traffic arrives. The advertised and acceptable latencies are part of PCIe capability negotiation, so a generic latency number should not be applied to every motherboard, GPU, SSD or network adapter.
L1.1 and L1.2 extend the L1 power-saving model
Modern PCIe implementations can support L1 substates, commonly L1.1 and L1.2. These allow additional link circuitry and clocking behavior to be quiesced beyond basic L1 where the platform and both ends of the link support the required mechanisms.
Intel platform documentation explicitly ties deeper PCIe link states to deeper package idle opportunities on supported processors. This is why disabling ASPM can increase platform idle power even when the endpoint itself appears idle: the PCIe link can prevent other parts of the platform from reaching their deepest supported low-power conditions.
Windows exposes link-state policy through the power framework
Windows includes a PCI Express Link State Power Management policy. Microsoft documents policy levels that range from no ASPM power saving through moderate and maximum power-saving behavior. The visible power-plan setting is policy; the actual state reached still depends on hardware, firmware and driver/platform support.
This setting should not be treated as a universal gaming-performance switch. ASPM changes idle-link power behavior and introduces state-exit latency, but that does not establish a measurable FPS or input-latency change for an arbitrary PC. A performance claim needs measurement on the exact workload and platform.
Linux can manage ASPM, but firmware remains part of the picture
The Linux PCIe stack can control ASPM when platform support permits it, and Linux exposes ASPM policy through the PCIe subsystem. Current kernel documentation also makes an important distinction for the pcie_aspm=off boot option: it tells Linux not to touch ASPM configuration, leaving firmware configuration unchanged; it does not necessarily prove that every link is electrically forced out of ASPM.
The kernel also documents a force option for hardware that does not claim ASPM support and explicitly warns that forcing ASPM can cause system lockups. That warning is a good boundary for troubleshooting: unsupported force-enabling is not a normal power-optimization recommendation.
ASPM is not the same thing as PCIe speed, width, or device power state
ASPM does not change a PCIe x16 link into x8, change Gen 5 into Gen 4, or define the device's own D0 through D3 power state. Generation and lane width describe transport capability; PCIe device power management describes device state; ASPM describes active-link idle behavior. These mechanisms can interact but are separate concepts.
Likewise, an AER error is not proof that ASPM is responsible. If a system has a repeatable PCIe stability problem, first identify the affected device and path, check documented firmware and driver issues, and change one relevant variable at a time. Disabling a power feature without evidence can hide the relationship rather than diagnose it.
When changing ASPM is actually useful
ASPM is worth investigating when you have a reproducible device or platform issue that correlates with link power-state transitions, or when measuring idle power on a system where deep package states are unexpectedly unavailable. In those cases, compare the documented firmware and OS policy, verify device capabilities, and measure before and after under the same conditions.
For a healthy desktop, the default platform policy is the appropriate baseline. Deeper link states exist because idle power matters, especially in mobile and energy-sensitive systems. Conversely, latency-sensitive engineering environments may intentionally constrain power states after measurement. Neither case justifies a universal rule that ASPM should always be enabled or always be disabled.
Sources
Primary and technical sources
Technical details can vary by exact model, firmware, and platform. These are the sources used for the factual claims in this article.
01 Microsoft Learn
Link state power management02 Linux Kernel Documentation
The kernel's command-line parameters03 Intel
PCI Express Power Management04 PCI-SIG / Intel-hosted specification
PCI Express Base Specification Revision 2.1
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