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PCIe standards utility

PCIe Link Bandwidth Calculator

Calculate theoretical one-direction PCI Express link capacity from PCIe generation and lane width. The result is a standards-level link figure, not a benchmark or prediction for a GPU, SSD, or other device.

Interactive calculation

Select a PCIe link

Choose the negotiated generation and lane width. The headline value is a theoretical one-direction link bandwidth after the generation's line-coding basis—not a prediction of device or application performance.

PCIe 5.0 ×16

63.02 GB/s

Theoretical bandwidth in one direction

After-coding bit rate
504.1 Gb/s
Bidirectional aggregate
126.0 GB/s
Raw transfer rate per lane
32 GT/s
Signaling / encoding
NRZ · 128b/130b

What the headline includes: lane count and the generation's documented line-coding/link-rate basis. Gen 1–2 use 8b/10b, Gen 3–5 use 128b/130b, and Gen 6–7 use PCI-SIG's published PAM4/FLIT directional link rates.

What it does not predict: GPU FPS, SSD benchmark throughput, latency, transaction-size effects, TLP headers, retries, software overhead, or any device-specific bottleneck.

Calculation basis

Generation assumptions

Headline bandwidth is one direction. Bidirectional aggregate is twice that number because PCIe is full duplex.

GenerationGT/s per laneSignaling / codingx16 one-wayMethod
PCIe 1.02.5NRZ · 8b/10b4 GB/sGT/s × 8b/10b efficiency
PCIe 2.05NRZ · 8b/10b8 GB/sGT/s × 8b/10b efficiency
PCIe 3.08NRZ · 128b/130b15.75 GB/sGT/s × 128b/130b efficiency
PCIe 4.016NRZ · 128b/130b31.51 GB/sGT/s × 128b/130b efficiency
PCIe 5.032NRZ · 128b/130b63.02 GB/sGT/s × 128b/130b efficiency
PCIe 6.064PAM4 · FLIT mode128 GB/sPCI-SIG published directional link rate
PCIe 7.0128PAM4 · FLIT mode256 GB/sPCI-SIG published directional link rate

Interpretation

What this number means

PCIe 1.0 and 2.0 use 8b/10b coding, so 20% of the line-coded bits are coding overhead. PCIe 3.0 through 5.0 use the more efficient 128b/130b scheme.

PCIe 6.0 and 7.0 use PAM4 signaling plus FLIT mode and FEC/CRC. For those generations, this calculator uses PCI-SIG's published directional link bandwidth rather than pretending the older coding-ratio formula still applies.

A 256-byte Gen 6/7 FLIT contains 236 bytes available for TLPs. The optional FLIT-space figure shown by the calculator is therefore a ceiling on TLP space—not application payload throughput. TLP headers, transaction size, retries, idle time, software, and the device itself still matter.

Standards references

Primary PCI-SIG sources

These public PCI-SIG references support the rate, coding, PAM4, and FLIT assumptions used by the calculator. They are standards references, not evidence of real device performance.

  1. 01 · PCI-SIG

    PCIe 3.0 encoding and earlier-generation bandwidth

  2. 02 · PCI-SIG

    PCIe 6.0 specification features and directional bandwidth

  3. 03 · PCI-SIG

    PCIe 6.0 FLIT mode and PAM4 FAQ

  4. 04 · PCI-SIG

    PCIe 7.0 data rate and bidirectional bandwidth

  5. 05 · PCI-SIG

    PCIe 7.0 FLIT layout compatibility with PCIe 6.0

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