1 · IBM
IBM Telum II (z17)8C / 16TMulti-chip module (DCM)
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Specifications
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| Specification | IBM Telum II (z17) |
|---|---|
| Overview | |
| Manufacturer | IBM |
| Launch date | 2025-06-17 |
| Market segment | server |
| Architecture | |
| Architecture | z/Architecture (Telum II, z17) |
| CPU process | Samsung 5nm EUV |
| Compute | |
| Cores | 8 |
| Threads | 16 |
| Clocks | |
| Base clock | 5.50 GHz |
| Cache | |
| L3 cache | 360 MB |
| Memory | |
| Memory support | DDR5 ECC RAIM, 2nd-gen on-chip AI accelerator |
| Platform | |
| Socket | Multi-chip module (DCM) |
References