CPU database reference

Verified catalog record

Zhaoxin KaiXian KX-7000 / KH-40000

Zhaoxin · Zhaoxin KaiXian KX-7000 / KH-40000

Zhaoxin KaiXian KX-7000 / KH-40000 processor reference with normalized architecture, compute, clocks, cache, memory, PCIe, power, and platform specifications.

Cores / threads: 8 / 8
Max boost: 3.70 GHz
Socket: LGA1700-compatible
Default TDP: 70 W

Benchmark

Measured performance reference

Benchmark results are comparable only within the exact same test. They do not represent total product quality.

Cinebench R23 Multi

CPU multi-core rendering benchmark

5,500points

#546 of 654

Rank among CPUs with a Cinebench R23 Multi score in the CTT dataset.

Technical data

Specifications

Only fields backed by the current normalized record are rendered; missing values stay absent rather than becoming N/A grids.

Overview

Manufacturer	Zhaoxin
Launch date	2024-04-02
Market segment	desktop

Architecture

Architecture	ShijiDadao (x86)
CPU process	TSMC 16nm FinFET

Compute

Cores	8
Threads	8

Clocks

Base clock	3.70 GHz
Maximum boost clock	3.70 GHz

Cache

L3 cache	32 MB

Memory

Memory support	DDR5-4800, DDR4-3200

Integrated Graphics

Integrated graphics	Zhaoxin C-1080 (integrated)

Power

Default TDP	70 W

Platform

Socket	LGA1700-compatible

Sources

Specification provenance

No public source record is available.

Useful next steps selected from the same technical reference and publication system.

Compatibility & upgrades

RAM Compatibility Explained: DDR Generation, DIMM Type, Capacity, Channels, XMP/EXPO, QVLs, and CPU/Motherboard Limits

Understand how DDR generation, DIMM type, CPU memory-controller limits, motherboard implementation, channels, module population, XMP/EXPO profiles, and QVL testing combine to determine real RAM compatibility.

Tool

DDR Memory Latency Calculator

Convert DDR data rate and CAS latency cycles into CAS timing in nanoseconds.

Technical guide

DDR Memory Speed and CAS Latency Explained: MT/s, MHz, CL, and Nanoseconds

Understand DDR memory data rate, underlying clock frequency, CAS latency in cycles, and how to convert CL into nanoseconds without mistaking it for total memory latency.