CPU database reference

Verified catalog record

Intel Xeon E5-2699 v3 (Haswell-EP)

Intel · Intel Xeon E5-2699 v3 (Haswell-EP)

Intel Xeon E5-2699 v3 (Haswell-EP) processor reference with normalized architecture, compute, clocks, cache, memory, PCIe, power, and platform specifications.

Cores / threads: 18 / 36
Max boost: 3.60 GHz
Socket: LGA2011-3
Default TDP: 145 W

Benchmark

Measured performance reference

Benchmark results are comparable only within the exact same test. They do not represent total product quality.

Cinebench R23 Multi

CPU multi-core rendering benchmark

19,500points

#288 of 654

Rank among CPUs with a Cinebench R23 Multi score in the CTT dataset.

Technical data

Specifications

Only fields backed by the current normalized record are rendered; missing values stay absent rather than becoming N/A grids.

Overview

Manufacturer	Intel
Launch date	2014-09-08
Market segment	server

Architecture

Architecture	Haswell-EP
CPU process	Intel 22nm CMOS

Compute

Cores	18
Threads	36

Clocks

Base clock	2.30 GHz
Maximum boost clock	3.60 GHz

Cache

L3 cache	45 MB

Memory

Memory support	DDR4-2133 quad-channel ECC

Power

Default TDP	145 W

Platform

Socket	LGA2011-3

Sources

Specification provenance

No public source record is available.

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Hardware reference

Intel Xeon E5-2699 v3 specifications

Intel Xeon E5-2699 v3 CPU specifications: Xeon, LGA2011-v3, 18 cores/36 threads.

Compatibility & upgrades

RAM Compatibility Explained: DDR Generation, DIMM Type, Capacity, Channels, XMP/EXPO, QVLs, and CPU/Motherboard Limits

Understand how DDR generation, DIMM type, CPU memory-controller limits, motherboard implementation, channels, module population, XMP/EXPO profiles, and QVL testing combine to determine real RAM compatibility.

Tool

DDR Memory Latency Calculator

Convert DDR data rate and CAS latency cycles into CAS timing in nanoseconds.

Technical guide

DDR Memory Speed and CAS Latency Explained: MT/s, MHz, CL, and Nanoseconds

Understand DDR memory data rate, underlying clock frequency, CAS latency in cycles, and how to convert CL into nanoseconds without mistaking it for total memory latency.