CPU Cache Coherency Explained: Cache Lines, MESI States, Ownership, and False Sharing

Modern CPUs use caches because repeatedly reaching main memory would be far slower than serving frequently used data close to the execution cores. A multicore design can therefore have several cached copies of data in flight at once: private caches near individual cores and additional cache capacity elsewhere in the hierarchy.

The problem appears when one core modifies data that another core has cached. Without a coherence mechanism, different cores could continue using incompatible cached copies of the same memory. Coherence protocols track cache-line state and coordinate ownership, invalidation and data movement so the cache hierarchy does not behave like a collection of unrelated memories.

Caches do not normally track each C or C++ variable as an independent coherence object. They move and manage fixed-size cache lines. AMD software-optimization documentation gives a concrete x86 example: a naturally aligned 64-byte data-cache line is treated as a unit, and modifying any byte marks that line as modified.

That distinction matters because two logically unrelated variables can occupy the same line. Hardware sees accesses to the line, not the programmer’s intent about which field belongs to which thread. It also means that a cache-line transfer or invalidation should not be described as an automatic trip to DRAM; another cache or another level of the hierarchy may be involved depending on the processor and state.

Intel’s architecture manual describes MESI—Modified, Exclusive, Shared and Invalid—as the cache protocol used to maintain consistency across its relevant data and unified caches. In the conceptual model, a Shared line must gain exclusive ownership before that cache can modify it, while an Exclusive clean line can be written without first invalidating another valid cached copy because no peer copy exists.

MESI is best used as a vocabulary for the state transitions a coherent system needs, not as a transistor-level blueprint for every current processor. Commercial CPUs can use protocol extensions, extra states, directory information, snoop filters and different interconnect or topology mechanisms. Those implementation details can change how coherence traffic is located and transported without changing the basic reason coherence exists.

False sharing occurs when threads modify different variables that happen to reside on the same cache line. The variables may be logically independent, but the coherence machinery still tracks the whole line. Ownership can therefore move or peer copies can be invalidated as the threads write their separate fields.

AMD explicitly documents this mechanism and recommends separating per-thread data, giving 64-byte alignment as an example for the processors covered by that guide. Intel’s current optimization material likewise describes unnecessary cache invalidations and updates when multiple threads contend for different variables in one line. The actual penalty is workload- and topology-dependent, so there is no honest universal percentage to subtract from performance.

L1, L2 and L3 labels describe levels in a cache hierarchy and are commonly discussed in terms of capacity, latency, sharing and inclusivity behavior. Coherence describes how cached copies are coordinated. Memory consistency describes rules about the ordering and visibility of memory operations. These subjects interact, but collapsing them into one concept creates misleading explanations.

The practical mental model is simple: caches make copies useful, cache lines define the granularity, and coherence keeps those copies coordinated when multiple cores participate. MESI provides a compact conceptual vocabulary for that coordination. For real performance questions, the next step is measurement on the actual processor and workload rather than extrapolating from protocol names.